Logic fault simulation on a vector hypercube multiprocessor
C3P Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2
Fault simulation on massively parallel SIMD machines: algorithms, implementations and results
Journal of Electronic Testing: Theory and Applications
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Workload Distribution in Fault Simulation
Journal of Electronic Testing: Theory and Applications
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Data parallel-fault simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A parallel algorithm for fault simulation based on PROOFS
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
GPU Cluster for High Performance Computing
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
GPGPU: general-purpose computation on graphics hardware
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
ACM SIGGRAPH 2007 courses
MARS: A Multiprocessor-Based Programmable Accelerator
IEEE Design & Test
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Introduction to GPU programming for EDA
Proceedings of the 2009 International Conference on Computer-Aided Design
Taming irregular EDA applications on GPUs
Proceedings of the 2009 International Conference on Computer-Aided Design
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Highly parallel decoding of space-time codes on graphics processing units
Allerton'09 Proceedings of the 47th annual Allerton conference on Communication, control, and computing
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GPU-Based Parallelization for Fast Circuit Optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Exploring high throughput computing paradigm for global routing
Proceedings of the International Conference on Computer-Aided Design
Accelerating RTL simulation with GPUs
Proceedings of the International Conference on Computer-Aided Design
GPU-based n-detect transition fault ATPG
Proceedings of the 50th Annual Design Automation Conference
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On the automatic generation of GPU-oriented software applications from RTL IPs
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Hi-index | 0.00 |
In this paper, we explore the implementation of fault simulation on a Graphics Processing Unit (GPU). In particular, we implement a fault simulator that exploits thread level parallelism. Fault simulation is inherently parallelizable, and the large number of threads that can be computed in parallel on a GPU results in a natural fit for the problem of fault simulation. Our implementation fault-simulates all the gates in a particular level of a circuit, including good and faulty circuit simulations, for all patterns, in parallel. Since GPUs have an extremely large memory bandwidth, we implement each of our fault simulation threads (which execute in parallel with no data dependencies) using memory lookup. Fault injection is also done along with gate evaluation, with each thread using a different fault injection mask. All threads compute identical instructions, but on different data, as required by the Single Instruction Multiple Data (SIMD) programming semantics of the GPU. Our results, implemented on a NVIDIA GeForce GTX 8800 GPU card, indicate that our approach is on average 35 x faster when compared to a commercial fault simulation engine. With the recently announced Tesla GPU servers housing up to eight GPUs, our approach would be potentially 238× faster. The correctness of the GPU based fault simulator has been verified by comparing its result with a CPU based fault simulator.