Logic fault simulation on a vector hypercube multiprocessor

Authors:
F. Ozguner;C. Aykanat;O. Khalid
Affiliations:
Department of Electrical Engineering, The Ohio State University, Columbus, Ohio;Department of Electrical Engineering, The Ohio State University, Columbus, Ohio;Department of Electrical Engineering, The Ohio State University, Columbus, Ohio
Venue:
C3P Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2
Year:
1989

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Abstract

Fault simulation is the process of simulating the response of a logic circuit to input patterns in the presence of all possible single faults and is an essential part of test generation for VLSI circuits. Parallelization of the deductive and parallel simulation methods, on a hypercube multiprocessor and vectorization of the parallel simulation method are described. Experimental results are presented.