Parallel algorithms for power estimation

Authors:
Victor Kim;Prithviraj Banerjee
Affiliations:
Center for Parallel and Distributed Computing, Dept. of Electrical and Computer Engineering, Northwestern University, Evanston, Illinois;Center for Parallel and Distributed Computing, Dept. of Electrical and Computer Engineering, Northwestern University, Evanston, Illinois
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

Sev eral tec hniques currently exist for estimating the pow er dissipation of combinational and sequen tialcircuits using exhaustive sim ulation,Monte Carlo sampling, and probabilistic estimation. Exhaustive sim ulation and Monte Carlo sampling techniques can be highly reliable but often require long runtimes. This paper presents a comprehensive study of pattern-p artitioning and circuit-p artitioning parallelization schemes for those tw o methodologies in the con text of distributed-memory multiprocessing systems. Issues in pip eline dev ent-driv en simulation and dynamic load balancing are addressed. Experimental results are presented for an IBM SP-2 system and a netw ork of HP-9000 workstations. F or instance, runtimes have been reduced from over 3 hours to under 20 minutes in one case.