Logic fault simulation on a vector hypercube multiprocessor
C3P Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2
Hierarchical multi-level fault simulation of large systems
Journal of Electronic Testing: Theory and Applications
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
An integrated design environment for performance and dependability analysis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multiple Experiment Environments for Testing
Journal of Electronic Testing: Theory and Applications
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
A new architectural-level fault simulation using propagation prediction of grouped fault-effects
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor
Proceedings of the IEEE International Test Conference on Test and Design Validity
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
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There is a growing demand to validate and test designs that integrate a multitude of discrete, standard and commercial off the shelf (COTS) components and software. Often, the proprietary nature of COTS further complicates the validation process by prohibiting designers from implementing a robust test and validation strategy. In order to preserve a vendor's intellectual property, a customer is often provided a high level model, with limited access to its internals. This limitation may preclude a customer from fully exercising their embedded designs, which may create safety issues for some embedded systems.The increasing use of high level models is creating a need for tools that are capable of testing and validating COTS components in conjunction with an engineer's more detailed design. Unfortunately, simulation tools currently available are incapable of simulating multilevel designs, which include gate, RTL and behavioral levels. Those tools that do attempt to solve these problems resort to merging simulators together, each targeted at handling a specific level of abstraction. This approach incurs high communication overhead between simulators, as well as impaired observation and accuracy.