The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Hardware acceleration of logic simulation using a data flow microarchitecture
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Performance analysis and design of a logic simulation machine
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A vector hardware accelerator with circuit simulation emphasis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Boolean comparison by simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Proteus-1: a general accelerator for CAD
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Parallel Discrete Event Simulation Using Shared Memory
IEEE Transactions on Software Engineering
HAL; A block level hardware logic simulator
25 years of DAC Papers on Twenty-five years of electronic design automation
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient circuit partitioning algorithms for parallel logic simulation
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Load Balancing in a Hybrid ATPG Environment
IEEE Transactions on Computers
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
State of the art in parallel simulation
WSC '92 Proceedings of the 24th conference on Winter simulation
Parallel gate-level circuit simulation on shared memory architectures
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Use of embedded scheduling to compile VHDL for effective parallel simulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Parallel logic simulation on a network of workstations using parallel virtual machine
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic simulation system using simulation processor (SP)
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Clock even suppression algorithm of VELVET and its application to S-820 development
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Parallel discrete event simulation: a case study
ANSS '85 Proceedings of the 18th annual symposium on Simulation
A technique for distributed execution of design automation tools
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A hardware engine for analogue mode simulation of MOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Speed up techniques of logic simulation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAL II: a mixed level hardware logic simulation system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Optimal performance of distributed simulation programs
WSC '87 Proceedings of the 19th conference on Winter simulation
Logic emulation with virtual wires
Readings in hardware/software co-design
Logic Simulation Engines in Japan
IEEE Design & Test
Systems with Low Distributed Simulation Overhead
IEEE Transactions on Parallel and Distributed Systems
Benchmarking Parallel Processing Platforms: An Applications Perspective
IEEE Transactions on Parallel and Distributed Systems
The Speedup Performance of an Associative Memory Based Logic Simulator
PaCT '999 Proceedings of the 5th International Conference on Parallel Computing Technologies
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
Functional models for VLSI design
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Ultimate: A hardware logic simulation engine
DAC '84 Proceedings of the 21st Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
Massively parallel array processor for logic, fault, and design error simulation
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Events suppression technique for high performance VHDL simulation
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Parallel switch-level simulation for VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
Hardware design and description languages in IBM
IBM Journal of Research and Development
Using a hardware simulation engine for custom MOS structured designs
IBM Journal of Research and Development
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
Methodology for & results from the use of a hardware logic simulation engine for fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Place and route for massively parallel hardware-accelerated functional verification
Proceedings of the International Conference on Computer-Aided Design
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The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. This paper introduces the YSE and describes its top-level architecture.