Efficient circuit partitioning algorithms for parallel logic simulation

Authors:
S. Patil;P. Banerjee;C. Polychronopoulos
Affiliations:
Center for Reliable and High Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL;Center for Reliable and High Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL;Center for Supercomputing, Research and Development, Talbot Laboratory, University of Illinois, Urbana, IL
Venue:
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Year:
1989

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Abstract

General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. This paper addresses logic simulation on parallel machines by exploiting the concurrency in the circuit being simulated (called data parallelism) as opposed to exploiting parallelism inherent in the simulation algorithm itself (called functional parallelism). The most crucial step in obtaining the maximum parallelism using data parallelism is the partitioning of circuit elements. We introduce a cost function which tries to model the simulation of a logic circuit in a parallel environment. The cost function tries to estimate the parallel run time for logic simulation given the processor assignment and the underlying multiprocessor architecture. We then present different heuristic algorithms to partition the circuit and evaluate the efficiency of these algorithms using the proposed cost function. Partitioning algorithms for both event-driven and compiled code simulation are given.