ACM Transactions on Programming Languages and Systems (TOPLAS)
Faster architectural simulation through parallelism
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics for parallelism and abstraction level in digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
The incorporation of functional level element routines into an existing digital simulation system
DAC '80 Proceedings of the 17th Design Automation Conference
Analysis of cache invalidation patterns in multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient circuit partitioning algorithms for parallel logic simulation
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Efficient parallel logic simulation techniques for the connection machine
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
IEEE Transactions on Parallel and Distributed Systems
Potential performance of parallel conservative simulation of VLSI circuits and systems
ANSS '92 Proceedings of the 25th annual symposium on Simulation
1988 Design Automation Conference: Guest Editorial
IEEE Design & Test
Parallel Distributed-Time Logic Simulation
IEEE Design & Test
Benchmarking Parallel Processing Platforms: An Applications Perspective
IEEE Transactions on Parallel and Distributed Systems
The Speedup Performance of an Associative Memory Based Logic Simulator
PaCT '999 Proceedings of the 5th International Conference on Parallel Computing Technologies
Some Recent Advances in Software and Hardware Logic Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Parallel switch-level simulation for VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
Efficiently unifying parallel simulation techniques
Proceedings of the 44th annual Southeast regional conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
| Hi-index | 0.00 |
Three parallel algorithms for logic simulation have been developed and implemented on a general purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speed-ups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled mode algorithm which achieves speed-ups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between 1 to 3 times faster than the conventional event-driven algorithm using 1 processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.