Circuit simulation on the connection machine
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Conservative Circuit Simulation on Multiprocessor Machines
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Stream Computations Organized for Reconfigurable Execution (SCORE)
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Design and Implementation of a Parallel Verilog Simulator: PVSim
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
GraphStep: A System Architecture for Sparse-Graph Algorithms
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Anton, a special-purpose machine for molecular dynamics simulation
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the 45th annual Design Automation Conference
A First-Passage Kinetic Monte Carlo algorithm for complex diffusion-reaction systems
Journal of Computational Physics
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A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70脳 faster than FPGA tools, with a circuit speed 5.8脳 slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range in the number of processor cores. We also demonstrate tool scalability to very large circuits, synthesizing, placing, and routing a 驴1.6 million gate random circuit in 54 min.