ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient algorithms for distributed snapshots and global virtual time approximation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Clustered time warp and logic simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Parallel and distributed VHDL simulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel discrete-event simulation applications
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Event reconstruction in time warp
Proceedings of the eighteenth workshop on Parallel and distributed simulation
A component-based simulation layer for JAMES
Proceedings of the eighteenth workshop on Parallel and distributed simulation
A non-fragmenting partitioning algorithm for hierarchical models
Proceedings of the 38th conference on Winter simulation
Compiled code in distributed logic simulation
Proceedings of the 38th conference on Winter simulation
A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures
On the scalability and dynamic load-balancing of optimistic gate level simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A parallel logic simulation framework: study, implementation, and performance
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
On the scalability and dynamic load balancing of parallel Verilog simulations
Winter Simulation Conference
A Multi-State Q-Learning Approach for the Dynamic Load Balancing of Time Warp
PADS '10 Proceedings of the 2010 IEEE Workshop on Principles of Advanced and Distributed Simulation
Recognizing and simulating sketched logic circuits
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part III
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
| Hi-index | 0.00 |
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the designof modern digital systems. Verification engineers can simulatehardware in order to verify its performance and correctnesswith help of an HDL. However, simulation can'tkeep pace with the growth in size and complexity of circuitsand has become a bottleneck of the design process. DistributedHDL simulation on a cluster of workstations hasthe potential to provide a cost-effective solution to this problem.In this paper, we describe the design and implementationof DVS, an object-oriented framework for distributedVerilog simulation. Verilog is an HDL which sees wide industrialuse. DVS is an outgrowth of Clustered Time Warp,originally developed for logic simulation. The design of theframework emphasizes simplicity and extensibility and aimsto accommodate experiments involving partitioning and dynamicload balancing. Preliminary results obtained by simulatinga 16bit multiplier are presented.