Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
A new approach to the minimum cut problem
Journal of the ACM (JACM)
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel and Distribution Simulation Systems
Parallel and Distribution Simulation Systems
Evaluation of Parallel Logic Simulation Using DVSIM
HICSS '96 Proceedings of the 29th Hawaii International Conference on System Sciences Volume 1: Software Technology and Architecture
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
Design and Implementation of a Parallel Verilog Simulator: PVSim
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
| Hi-index | 0.00 |
We present a parallel logic simulation framework aiming at more then one simulation language, not only some special. After investigating a number of research issues in parallel logic simulation, we study these key techniques including general parallelization method, code portioning, and practical synchronization algorithm. Based on ArchSim (a system-level parallel simulation platform), the framework can run on heterogeneous computing environments. By using the framework, we parallelize two logic simulation languages: SystemC and Verilog. Then, we design a pipelined multi-stage benchmark to evaluate the framework. Encouraging test results indicate that speedup gradually approaches to the linear growth with the computation complexity or the number of stages increasing. Another SoC application shows that speedup of the parallel logic simulation framework is almost the same with the shared-memory scheme. To sum up, by using our framework, a logic simulation language is easily parallelized to gain an excellent speedup.