A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
The FAST methodology for high-speed SoC/computer simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
On Determining How Many Computers to Use in Parallel VLSI Simulation
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
A parallel logic simulation framework: study, implementation, and performance
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
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Parallel HDL simulation is an efficient method toaccelerate the verification process of large complex VLSIsystem design. This paper presents a parallel Verilogsimulator - PVSim, which bases on optimisticasynchronous parallel simulation algorithm and MPIlibrary. A new module-based simulation componentmapping method is proposed. And an efficient module-basedpartition algorithm combined with pre-simulationpartition algorithm is adopted. This paper introduces thearchitecture of PVSim, the Verilog component mappingtechniques, the distributed simulation cycle arrangementand the circuit partition algorithm in detail. Experimentalresults show that PVSim can get promising speedup, aswell as distributed workload and communication costacross processors.