Efficient algorithms for distributed snapshots and global virtual time approximation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Approximate nearest neighbors: towards removing the curse of dimensionality
STOC '98 Proceedings of the thirtieth annual ACM symposium on Theory of computing
Architecture driven circuit partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Parallel Optimistic Logic Simulation with Event Lookahead
ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
Design and Implementation of a Parallel Verilog Simulator: PVSim
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
XTW, A Parallel and Distributed Logic Simulator
Proceedings of the 19th Workshop on Principles of Advanced and Distributed Simulation
A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
Automatic generation of synthetic sequential benchmark circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Parallel discrete event simulation has been established as a technique which has great potential to speed up the execution of gate level circuit simulation. A fundamental problem posed by a parallel environment is the decision of whether it is best to simulate a particular circuit sequentially or on a parallel platform. Furthermore, in the event that a circuit should be simulated on a parallel platform, it is necessary to decide how many computing nodes should be used on the given platform. In this paper we propose a machine learning algorithm as an aid in making these decisions. The algorithm is based on the well-known K-Nearest Neighbor algorithm. After an extensive training regime, it was shown to make a correct prediction 99% of the time on whether to use a parallel or sequential simulator. The predicted number of nodes to use on a parallel platform was shown to produce an average execution time which was not more than 12% of the smallest execution time. The configuration which resulted in the minimal execution time was picked 61% of the time.