Architecture driven circuit partitioning

Authors:
Chau-Shen Chen;C. L. Liu;Ting Ting Hwang
Affiliations:
National Tsing Hua Univ., HsinChu, Taiwan;National Tsing Hua Univ., HsinChu, Taiwan;National Tsing Hua Univ., HsinChu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2001

Citing 0
Cited 3

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation

Simulation
On Determining How Many Computers to Use in Parallel VLSI Simulation

PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation

Quantified Score

Hi-index	0.02

Visualization

Abstract

In this paper, we propose an architecture driven partitioning algorithm for netlists with multiterminal nets. Our target architecture is a multifield-programmable gate array (FPGA) emulation system with folded-Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize routability. To that end, we introduce a new cost function: the average number of pseudoterminals per net in a multiway cut. Experimental result shows that our algorithm is very effective in terms of the number of chips used and routability as compared to other methods.