ACM Transactions on Programming Languages and Systems (TOPLAS)
Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
The connection machine
Performance analysis and design of a logic simulation machine
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics for parallelism and abstraction level in digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient distributed event-driven simulations of multiple-loop networks
Communications of the ACM
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Data parallel simulation using time-warp on the connection machine
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Time warp on a shared memory multiprocessor
Transactions of the Society for Computer Simulation International
Efficient parallel logic simulation techniques for the connection machine
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Design of a scalable parallel switch-level simulator for VLSI
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Distributed and parallel demand driven logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On a parallel partitioning technique for use with conservative parallel simulation
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
An empirical study of on-chip parallelism
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic simulation system using simulation processor (SP)
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Ravel: assigned-delay compiled-code logic simulation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Parallel logic and fault simulation algorithms for shared memory vector machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A logic simulation engine based on a modified data flow architecture
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Exploiting parallelism in a switch-level simulation machine
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAL II: a mixed level hardware logic simulation system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Deterministic Processor Scheduling
ACM Computing Surveys (CSUR)
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Parallel Logic Simulation Using Time Warp on Shared-Memory Multiprocessors
Proceedings of the 8th International Symposium on Parallel Processing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
A data-driven multiprocessor for switch-level simulation of vlsi circuits
A data-driven multiprocessor for switch-level simulation of vlsi circuits
Parallel mixed-level simulation of digital circuits using virtual time
Parallel mixed-level simulation of digital circuits using virtual time
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Clustered time warp and logic simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
The APOSTLE simulation language: granularity control and performance data
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Conservative circuit simulation on shared-memory multiprocessors
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Perils and pitfalls of parallel discrete-event simulation
WSC '96 Proceedings of the 28th conference on Winter simulation
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
Optimizing communication in time-warp simulators
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
Shared memory implementation of a parallel switch-level circuit simulator
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
Parallel and distributed VHDL simulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Automatic Parallelization of Compiled Event Driven VHDL Simulation
IEEE Transactions on Computers
On Rolling Back and Checkpointing in Time Warp
IEEE Transactions on Parallel and Distributed Systems
Demand-driven logic simulation using a network of loosely coupled processors
Journal of Systems Architecture: the EUROMICRO Journal
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Event reconstruction in time warp
Proceedings of the eighteenth workshop on Parallel and distributed simulation
Parallel verilog simulation: architecture and circuit partition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
XTW, a parallel and distributed logic simulator
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Framework for Distributed Simulation of Asynchronous Handshake Circuits
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
A non-fragmenting partitioning algorithm for hierarchical models
Proceedings of the 38th conference on Winter simulation
A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
On Determining How Many Computers to Use in Parallel VLSI Simulation
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A New Algorithm for VHDL Parallel Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reversible Parallel Discrete Event Formulation of a TLM-Based Radio Signal Propagation Model
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
Automatic partitioner for behavior level distributed logic simulation
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Can PDES scale in environments with heterogeneous delays?
Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation
| Hi-index | 0.00 |
Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution time required by simulation is becoming more and more significant. Faster logic simulators will have an appreciable economic impact, speeding time to market while ensuring more thorough system design testing. One approach to this problem is to utilize parallel processing, taking advantage of the concurrency available in the VLSI system to accelerate the logic simulation task.Parallel logic simulation has received a great deal of attention over the past several years, but this work has not yet resulted in effective, high-performance simulators being available to VLSI designers. A number of techniques have been developed to investigate performance issues: formal models, performance modeling, empirical studies, and prototype implementations. Analyzing reported results of these techniques, we conclude that five major factors affect performance: synchronization algorithm, circuit structure, timing granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the results and present directions for future research in the field.