ACM Transactions on Programming Languages and Systems (TOPLAS)
Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
Computer aids for VLSI design
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Introduction to algorithms
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IEEE Spectrum
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Heterogenous distributed simulation
WSC '88 Proceedings of the 20th conference on Winter simulation
A 4.2bsd Interprocess Communication Primer
A 4.2bsd Interprocess Communication Primer
Effect of communication overheads on Time Warp performance: an experimental study
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Predicting the future: resource requirements and predictive optimism
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Dynamic load balancing of a multi-cluster simulator on a network of workstations
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel and distributed discrete event simulation: algorithms and applications
WSC '93 Proceedings of the 25th conference on Winter simulation
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
PADS '00 Proceedings of the fourteenth workshop on Parallel and distributed simulation
More enhancements of the simplescalar tool set
ACM SIGARCH Computer Architecture News
Demand-driven logic simulation using a network of loosely coupled processors
Journal of Systems Architecture: the EUROMICRO Journal
WCAE '00 Proceedings of the 2000 workshop on Computer architecture education
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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An approach for high performance parallel logic simulation on a local area network of workstation computers is discussed in this paper. The single, shared transmission medium often found in such networks places limitations on parallel execution, hence a reduction in the frequency of synchronization is pursued by combining a circuit partitioning methodology with a specific synchronization constraint. A consequence of the partitioning methodology is replication of objects between blocks of a partition. A partitioning procedure based on iterative improvement is described for reducing replication while preserving load balance. Two interprocessor synchronization techniques for parallel simulation are studied: conservative and optimistic synchronization. Experiments conducted on three large sequential circuits indicate that reasonable speedup is achievable for well-balanced partitions, and that optimistic synchronization provides a modest improvement in performance over conservative synchronization.