ACM Transactions on Programming Languages and Systems (TOPLAS)
Concurrent Access of Priority Queues
IEEE Transactions on Computers
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Parallel heap: an optimal parallel priority queue
The Journal of Supercomputing
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
On extending parallelism to serial simulators
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Effectiveness of global event queues in rollback reduction and load balancing
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Toward automatic parallelization of discrete event simulation programs
Toward automatic parallelization of discrete event simulation programs
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Symphony: a simulation backplane for parallel mixed-mode co-simulation of VLSI systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Automatic data distribution for composite grid applications
Scientific Programming - Special issue: High Performance Fortran comes of age
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
Shared memory implementation of a parallel switch-level circuit simulator
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
Case study: parallelizing a sequential simulation model
PADS '99 Proceedings of the thirteenth workshop on Parallel and distributed simulation
SPDP '95 Proceedings of the 7th IEEE Symposium on Parallel and Distributeed Processing
Logic Verification of Very Large Circuits Using Shark
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Proceedings of the 35th conference on Winter simulation: driving innovation
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We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.