Performance of a multiple-entry-node concurrent skew heap on shared-memory multiprocessor
ACM-SE 36 Proceedings of the 36th annual Southeast regional conference
PADS '00 Proceedings of the fourteenth workshop on Parallel and distributed simulation
Proceedings of the 35th conference on Winter simulation: driving innovation
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We present an efficient implementation of the parallel heap data structure on a bus-based Silicon Graphics multiprocessor GTX/4D. Parallel heap is theoretically the first heap-based data structure to have implemented an optimally scalable parallel priority queue on an exclusive-read exclusive-write parallel random access machine. We compared it with Rao-and-Kumar's concurrent heap and with the conventional serial heap accessed via a lock. The parallel heap outperformed others for fine-to-medium grains achieving speedups of two to four using six processors relative to the best sequential execution times. The concurrent heap, however, exhibited performance comparable only to the serial heap. As expected for coarser grain, the serial heap performed at par with or better than others.