Design of a scalable parallel switch-level simulator for VLSI
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
An empirical study of on-chip parallelism
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Maisie: A Language for the Design of Efficient Discrete-Event Simulations
IEEE Transactions on Software Engineering
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Shared memory implementation of a parallel switch-level circuit simulator
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
PADS '00 Proceedings of the fourteenth workshop on Parallel and distributed simulation
Simulating spatially explicit problems on high performance architectures
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Parallel Languages for Discrete-Event Simulation Models
IEEE Computational Science & Engineering
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This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.