MuSiC: an event-flow computer for fast simulation of digital systems
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The STE-264 accelerated electronic CAD system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Collecting Data About Logic Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis and design of a logic simulation machine
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Faster architectural simulation through parallelism
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics for parallelism and abstraction level in digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Massively parallel switch-level simulation: a feasibility study
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic simulation on massively parallel architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel logic level simulation of VLSI circuits
WSC '94 Proceedings of the 26th conference on Winter simulation
Distributed simulation for structural VHDL netlists
EURO-DAC '94 Proceedings of the conference on European design automation
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Potential performance of parallel conservative simulation of VLSI circuits and systems
ANSS '92 Proceedings of the 25th annual symposium on Simulation
Parallel switch-level simulation for VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
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The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speedups over standard software based logic simulators. Several commercial simulation engines have been produced to satisfy needs in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. The data contained in the paper includes information on subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.