Performance analysis and design of a logic simulation machine
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Boolean comparison by simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
HAL; A block level hardware logic simulator
25 years of DAC Papers on Twenty-five years of electronic design automation
Massively parallel switch-level simulation: a feasibility study
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic simulation on massively parallel architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Performance evaluation of an event-driven logic simulation machine
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
IEEE Transactions on Parallel and Distributed Systems
The IBM engineering verification engine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Parallel logic and fault simulation algorithms for shared memory vector machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A logic simulation engine based on a modified data flow architecture
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
MuSiC: an event-flow computer for fast simulation of digital systems
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Modeling switch-level simulation using data flow
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Switch-level simulation of VLSI using a special-purpose data-driven computer
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Evon: an extended von Neumann model for parallel processing
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Optical interconnection systems for digital parallel processors
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
IEEE Design & Test
DEVS Formalism: A Framework for Hierarchical Model Development
IEEE Transactions on Software Engineering
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Ultimate: A hardware logic simulation engine
DAC '84 Proceedings of the 21st Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel processing, special-purpose hardware, and DA applications
CSC-83 Proceedings of the 1983 computer science conference
Massively parallel array processor for logic, fault, and design error simulation
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Some Recent Advances in Software and Hardware Logic Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
EURO-DAC '90 Proceedings of the conference on European design automation
Using a hardware simulation engine for custom MOS structured designs
IBM Journal of Research and Development
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Place and route for massively parallel hardware-accelerated functional verification
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
The Yorktown Simulation Engine (YSE) is a high speed special purpose parallel processor designed and built at the I.B.M. Thomas J. Watson Research Center to simulate the logical operation of large digital networks. A full YSE configuration simulates networks of up to 2,000,000 gates at a rate exceeding 3 billion gate computations per second, doing more simulation in just eight hours than an IBM 370/168 does in an entire year. This paper reviews gate-level logic simulation and describes the architecture and hardware implementation of the YSE. A companion paper by G. Pfister and E. Kronstadt discusses the YSE software.