Exclusive simulation of activity in digital networks
Communications of the ACM
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Hardware acceleration of logic simulation using a data flow microarchitecture
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Self-adjusting networks for VLSI simulations
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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The growing need for high-speed digital logic simulation is well-known and several special-purpose hardware architectures to provide this have, to date, been presented. This paper attempts to address the problems of high-speed simulation in a more systematic and detailed manner to achieve an enhanced performance from a simpler architecture. The proposed architecture is capable of providing all the facilities currently available in software logic simulators.