Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Ultimate: A hardware logic simulation engine
DAC '84 Proceedings of the 21st Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Modeling of intermediate node states in switch-level networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
A multiple-dominance switch-level model for simulation of short faults
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Oscillation control in logic simulation using dynamic dominance graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
| Hi-index | 14.98 |
Magnitude networks [1l, [2] have been used as a theoretical base for switch-level simulation of MOS VLSI circuits. We address in this paper the particular problem of evaluating the influence of switches in unknown state on the steady-state response of the network. A two-pass procedure based on local controllers attached to such switches is described and a hardware implementation is proposed which models magnitude networks as self-adjusting combinational circuits.