Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Introduction to VLSI Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
A MOS/LSI oriented logic simulator
DAC '81 Proceedings of the 18th Design Automation Conference
A set of programs for MOS design
DAC '81 Proceedings of the 18th Design Automation Conference
A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge
DAC '81 Proceedings of the 18th Design Automation Conference
MOSSIM: A switch-level simulator for MOS LSI
DAC '81 Proceedings of the 18th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Computational Aspects of VLSI
On a Ternary Model of Gate Networks
IEEE Transactions on Computers
A Note on Three-Valued Logic Simulation
IEEE Transactions on Computers
IEEE Transactions on Computers
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
IEEE Transactions on Computers
Self-adjusting networks for VLSI simulations
IEEE Transactions on Computers
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Switch-level simulation of VLSI using a special-purpose data-driven computer
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Switch-level bridging fault simulation in the presence of feedbacks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Switch level hot-carrier reliability enhancement of VLSI circuits
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Switch-level modeling of feedback faults using global oscillation control
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Algorithms for Switch Level Delay Fault Simulation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Switch-Level Algorithm for Simulation of Transients in Combinational Logic
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Parallel discrete-event simulation of population dynamics
Proceedings of the 40th Conference on Winter Simulation
A new modeling technique for mixed-mode simulation of CMOS circuits
Integration, the VLSI Journal
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic synthesis of computation interference constraints for relative timing verification
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Switch-level concurrent fault simulation based on a general purpose list traversal mechanism
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault injection into Verilog models for dependability evaluation of digital systems
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Verification of the power-down mode of analog circuits by structural voltage propagation
Analog Integrated Circuits and Signal Processing
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.