Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
IEEE Transactions on Computers
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
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In this paper we formalize a ternary model which is being used to study the behavior of binary sequential gate networks. We first describe a binary model which is capable of a detailed description of network behavior, but involves a number of steps that grows exponentially in the number of gates. The complexity of the ternary model is linear in the number of gates;however, only partial information is obtained in generaL A mathematical theory is developed making precise these two models and the comparison between them. A number of examples illustrate these results. This work generalizes previously reported research.