A Systematic Approach to Digital Logic Design
A Systematic Approach to Digital Logic Design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Programming aspects of VLSI: (preliminary version)
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An improved switch-level simulator for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
The second generation motis mixed-mode simulator
DAC '84 Proceedings of the 21st Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
On a Ternary Model of Gate Networks
IEEE Transactions on Computers
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
Toward a switching theory of CMOS circuits
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Corrections to "Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection"
IEEE Transactions on Computers
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We present algorithms and time complexity results for MOS switch-level simulation with particular reference to race detection. Under the switching model used in classical (Boolean) switching theory, we derive a linear-time race detection algorithm for switch-level circuits that have no feedback within a clock phase, and have unit fan-out. We show that the problem becomes NP-complete if fan-out of two or more is allowed. We Also relate this result to others that have recently been reported, using a different switching model.