Correspondence between ternary simulation and binary race analysis in gate networks
International Colloquium on Automata, Languages and Programming on Automata, languages and programming
Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
IEEE Transactions on Computers
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
On a Ternary Model of Gate Networks
IEEE Transactions on Computers
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
A unified framework for race analysis of asynchronous networks
Journal of the ACM (JACM)
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Beyond two
An accurate model for ambiguity delay simulation
EURO-DAC '90 Proceedings of the conference on European design automation
| Hi-index | 14.98 |
Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we prove a somewhat modified version of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of in the "multiple-winner" model, where - is the network N in which a delay has been inserted in each wire.