A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An accurate time delay model for large digital network simulation
DAC '76 Proceedings of the 13th Design Automation Conference
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Timing analysis for digital fault simulation using assignable delays
DAC '74 Proceedings of the 11th Design Automation Workshop
A portable and extendible testbed for distributed logic simulation
EURO-DAC '94 Proceedings of the conference on European design automation
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This paper presents a new approach for the accurate computation of ambiguously delayed waveforms which is implemented in the event-driven logic simulation system LDSIM. Six logic values are defined to be sets of up to four basic values. The mapping function representing the ambiguity delay model only manipulates these basic values. This principle results in a powerful and versatile ambiguity delay model that is clearly presented, easy to implement and guarantees correct delay computation of arbitrary six-valued waveforms with respect to the concept of superposition and causality.