Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An accurate model for ambiguity delay simulation
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI.