Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Logic verification system for very large computers using LSI's
DAC '79 Proceedings of the 16th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Timing analysis of computer hardware
IBM Journal of Research and Development
| Hi-index | 0.00 |
A Critical Path Delay Check System for designing computers is described. It calculates the critical path delay between the start and end points. It can be used in the early stage of design when, for example, the location of the components on a plug-in card has not yet been determined. Some algorithms for predicting delays are also introduced.