Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
The analog behavior of digital integrated circuits
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Switch-level delay models for digital MOS VLSI
25 years of DAC Papers on Twenty-five years of electronic design automation
Electrical optimization of PLAs
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
| Hi-index | 0.00 |
This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.