25 years of DAC Papers on Twenty-five years of electronic design automation
A multiple media delay simulator for MOS LSI circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
An experimental system for power/timing optimization of LSI chips
DAC '77 Proceedings of the 14th Design Automation Conference
Automated performance optimization of custom integrated circuits
Automated performance optimization of custom integrated circuits
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
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This work addresses the problem of improving an nMOS PLA's speed and power consumption through modifications to the transistor sizes in the PLA. A simplified model of gate delay (lumped RC model) is used that allows rapid estimation of delays thus allowing interactive computation of optimal transistor sizes. Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay. Both these minima are computed subject to bounds on the transistor sizes. A prototype electrical optimization tool was compared to the PLA generation tools in the Berkeley CAD tools package (eqntott and tpla). The maximum delay through a PLA can often be reduced by a factor of 2, and power consumption along the critical paths can be reduced by 10 - 30% without increasing maximum delay.