Some experimental results on placement techniques
DAC '76 Proceedings of the 13th Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Electrical optimization of PLAs
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing analysis of computer hardware
IBM Journal of Research and Development
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An experimental system of programs is described which places logic gates on a chip, globally wires the gates and then optimizes the power required to drive them. Further power reductions are realized by using power-oriented placement improvement techniques. A companion paper describes how the optimization is accomplished by using the timing requirements of the chip as constraints and assigning delays to the logic gates so that these constraints are met and the power is minimized.