The Geometry Engine: A VLSI Geometry System for Graphics
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Switch-level delay models for digital MOS VLSI
25 years of DAC Papers on Twenty-five years of electronic design automation
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
An electrical optimizer that considers physical layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Switch level random pattern testability analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Electrical optimization of PLAs
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SIMMOS: a multiple-delay switch-level simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
A new algorithm for transistor sizing in CMOS circuits
EURO-DAC '90 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay optimization of linear depth boolean circuits with prescribed input arrival times
Journal of Discrete Algorithms
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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TV and IA are timing analysis programs for nMOS VLSI designs. Based on the circuit obtained from existing circuit extractors, TV determines the minimum clock duty and cycle times. It calculates the direction of signal flow through all transistors before the timing analysis is performed. The timing analysis is breadth-first (block-oriented) and pattern independent, using the values stable, rise, fall, as well as information about clock qualification. TV has fast running time, small user input requirements, and the ability to offer the user valuable advice. IA (TV's Interactive Advisor) allows the user to quickly experiment with ways to increase circuit performance. Several delay models can be used; when compared to circuit simulation and fabricated chips, accuracies within 20% for most critical paths have been achieved.