Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
The ALGIC silicon compiler system: implementation, design experience and results
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ATV: an abstract timing verifier
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Formal verification of timing conditions
EURO-DAC '90 Proceedings of the conference on European design automation
| Hi-index | 0.00 |
The program SCAT is a new timing verifier within the ALGIC silicon compiler. It provides a precise assessment of the timing behaviour of the automatically generated LSI circuits by means of block-oriented statistical algorithms leading to a running time approximately linear to the number of circuit elements, which are emulated by delay time elements. Interconnect delays are handled by the same statistical model. Synchronous circuits are described by an appropriate coordinate transformation leading to an algorithm for the calculation of the minimum clock period. The special case of recursive structures is briefly mentioned.