SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
LASSIE: structure to layout for behavioral synthesis tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Application-specific microelectronics for mechatronic systems
EURO-DAC '92 Proceedings of the conference on European design automation
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In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom design style. Main components of the ALGIC system are a system monitor module, a parameterisable macrocell generator, an appropriate floorplanner with 100% routing solution including planar VDD/GND trees and a block-oriented timing verifier. One essential feature of the system is the high degree of integration between all program modules using the concept of abstract data types. The flexibility and performance of the whole system is demonstrated by real design examples in the field of DSP applications.