Formal verification of timing conditions

Authors:
Hans Eveking;Christoph Mai
Affiliations:
Institute f¨r Datentechnik, Technische Hochschule Darmstadt, D-6100 Darmstadt, Fed. Rep. of Germany;Institute f¨r Datentechnik, Technische Hochschule Darmstadt, D-6100 Darmstadt, Fed. Rep. of Germany
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 5
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Abstract

Most timing-verifiers are analytical tools that determine, e.g., the delays on all paths, etc. This paper presents a completely different approach: timing-verification is performed by means of the formal transformation of CHDL descriptions. The principles of this procedure are presented and performance results of an implementation are given.