Plug-in timing models for an abstract timing verifier

Authors:
David E. Wallace;Carlo H. Séquin
Affiliations:
Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

Citing 6
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Abstract

We have developed the concept of an abstract timing verifier that accepts plug-compatible timing models in a common framework containing the scheduling algorithms and the user interface. Depending on the design phase and the particular level of design representation used, the most suitable timing model can be plugged into this framework and operated in a standard way.This paper formally introduces the abstract timing model and defines the operations that need to be carried out in such models. It discusses the models used in existing commercial timing verifiers in this context and compares them against some new and modified models. It presents some guidelines for the extension of this library of timing models.