Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Timing Analysis Using Functional Analysis
IEEE Transactions on Computers
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Timing Models for MOS Circuits
Timing Models for MOS Circuits
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The new SLOCOP-II timing verification system for the accurate performance analysis of MOSVLSI circuits is being presented. The algorithms in SLOCOP-II solve the serious problem of "false paths" that occur in all existing timing verifiers, by taking into account the logic functionallity of the circuits at hand. To allow this for custom MOSVLSI designs, new event determination algorithms based on binary decision tree (BDT) have been developed and are presented in this paper. The algorithms to avoid the indication of "false longest delay paths" can take a long calculation time. There fore two new techniques have been developed: 1) by preprocessing the constrained event graph, compiled code can be generated that can execute orders of magnitude faster and 2) by exploiting the hierarchy available in circuits. These algorithms have been implemented in the SLOCOP-II timing verification system. Results and comparative cpu-times on parameterised modules in the CATHEDRAL-II library are presented in the paper.