Timing analysis in precharge/unate networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Critical path selection for performance optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing verification on a 1.2M-device full-custom CMOS design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Is redundancy necessary to reduce delay
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
The exact solution of timing verification
EURO-DAC '92 Proceedings of the conference on European design automation
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Exact path sensitization in timing analysis
EURO-DAC '94 Proceedings of the conference on European design automation
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
AFTA: a formal delay model for functional thinking analysis
Proceedings of the conference on Design, automation and test in Europe
Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
SLOCOP-II: a versatile timing verification system for MOSVLSI
EURO-DAC '90 Proceedings of the conference on European design automation
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improvements on the detection of false paths by using unateness and satisfiability
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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This paper describes a new method for solving the false path problem in static timing analysis of acyclic, combinational circuits. The conditions under which a path is false are accurately defined. The fact that these conditions explicitly take into account the dynamic behaviour of the circuit, constitutes the main contribution of the paper. An algorithm for computing the longest dynamically sensitizable paths in an acyclic, combinational circuit is presented.