On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Extended stuck-fault testability for combinational networks
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
On the interaction of functional and timing behaviour of combinational logic circuits
On the interaction of functional and timing behaviour of combinational logic circuits
Symbolic functional and timing verification of transistor-level circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
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We consider the false path problem on precharge/unate networks, more commonly known as dynamic CMOS networks. We demonstrate that the tight criterion of dynamic sensitization is robust on such networks, though it has been shown to be non-robust on general networks. Tighter bounds may be obtained on the length of the critical path in precharge/unate networks than in general static networks. We derive a dynamic programming procedure to find the longest dynamically sensitizable path in a precharge/unate network.