On the interaction of functional and timing behaviour of combinational logic circuits

Timing analysis in precharge/unate networks

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Accurate layout area and delay modeling for system level design

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Satisfiability models and algorithms for circuit delay computation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Event propagation for accurate circuit delay calculation using SAT

ACM Transactions on Design Automation of Electronic Systems (TODAES)

SAT based timing analysis for fixed and rise/fall gate delay models

Integration, the VLSI Journal