Hierarchical timing verification system
Computer-Aided Design
A path selection algorithm for timing analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing analysis in precharge/unate networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Critical path selection for performance optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Is redundancy necessary to reduce delay
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
The exact solution of timing verification
EURO-DAC '92 Proceedings of the conference on European design automation
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
Timing optimization by gate resizing and critical path identification
DAC '93 Proceedings of the 30th international Design Automation Conference
Dynamical identification of critical paths for iterative gate sizing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Exact path sensitization in timing analysis
EURO-DAC '94 Proceedings of the conference on European design automation
Path sensitization of combinational circuits and its impact on clocking of sequential systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interface timing verification drives system design
DAC '97 Proceedings of the 34th annual Design Automation Conference
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
SMT-based optimization for synchronous programs
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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The false path problem is often referred to as the problem of detecting the longest sensitizable path (A path which is not a false path is a sensitizable path). The term “false path” is not clearly defined. In this paper, we first give a clear and precise definition of a false path. Then the general false path problem is formulated. The general false path problem is to detect whether a given path (not necessarily the longest one) is a false path. We present an efficient algorithm for solving the general false path problem. We also propose another algorithm which generates all the possible sensitizable paths with the delays greater than a given threshold T. The efficiency and effectiveness of the proposed algorithm are demonstrated by the experimental results.Index Terms: Timing Verification, Logic Simulation, VLSI circuit, Timing Analysis, False path, Graph Theory.