On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Circuit delay models and their exact computation using Timed Boolean Functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Gate-level timing verification using waveform narrowing
EURO-DAC '94 Proceedings of the conference on European design automation
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Ravel: assigned-delay compiled-code logic simulation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
An advanced timing characterization method using mode dependecy
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A framework for estimating peak power in gate-level circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
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Accurate and efficient computation of delays is a central problem in computer-aided design of complex VLSI circuits. Delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. Although many different propagation conditions (PCs) have been proposed for delay computation, their properties and relationships have been far from clear. We present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of details. The most general model, called the exact of W0 model, specifies each event occurring in a circuit signal. A novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. For each waveform model, we drive the PCs that correctly capture the requirements under which an event propagates along a path. The waveform models and their PCs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. The relationships among the derived PCs and existing ones are analyzed in depth. It is proven that though many PCs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. This analysis further enables us to derive new and useful PCs. We describe such a PC, called safe static. Experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff.