A framework for estimating peak power in gate-level circuits

Authors:
Diganchal Chakraborty;P. P. Chakrabarti;Arijit Mondal;Pallab Dasgupta
Affiliations:
Indian Institute of Technology Kharagpur, India;Indian Institute of Technology Kharagpur, India;Indian Institute of Technology Kharagpur, India;Indian Institute of Technology Kharagpur, India
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS'89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.