Timing Analysis Using Functional Analysis
IEEE Transactions on Computers
Algorithms for multilevel logic optimization
Algorithms for multilevel logic optimization
Critical paths in circuits with level-sensitive latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Fast and accurate timing characterization using functional information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exponent monte carlo for quick statistical circuit simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Static timing analysis is a technique for estimating the delay of a design without electrical simulation. It is widely adopted in industry for timing verification and optimization. This chapter will overview the basics of static timing analysis.