On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Circuit structure relations to redundancy and delay: the KMS algorithm revisited
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Approximate timing analysis of combinational circuits under the XBD0 model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Proceedings of the conference on Design, automation and test in Europe
False timing path identification using ATPG techniques and delay-based information
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Efficient static timing analysis and applications using edge masks
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving the efficiency of static timing analysis with false paths
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
RTL analysis and modifications for improving at-speed test
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a new method for removing user-specified false subgraphs from timing analysis and circuit optimization. Given a timing graph and a list of specified false paths, false subpaths, or false subgraphs, we generate a new timing graph in which all specified false paths are removed using a process of node splitting and edge removal. We present the necessary and sufficient condition for splitting a node, and show that the number of nodes that must be added to the timing graph is linear with the size of the false path specification. We also present an algorithm for finding the minimum set of nodes that must be split. Since this algorithm requires exponential run time for false subpaths and false subgraphs, we present a heuristic splitting approach which has linear worst-case run time, and where the number of added nodes is linear with the size of the false path specification. The heuristic approach was implemented and results are given for large industrial circuits.