EURO-DAC '92 Proceedings of the conference on European design automation
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Approximate timing analysis of combinational circuits under the XBD0 model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay estimation VLSI circuits from a high-level view
DAC '98 Proceedings of the 35th annual Design Automation Conference
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
A Methodology for Synthesis of Data Path Circuitse
IEEE Design & Test
Modeling Combinational Circuits Using Linear Word-level Structures
Automation and Remote Control
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier, the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined control inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.