Performance and testability interactions in logic synthesis
Performance and testability interactions in logic synthesis
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circuit delay models and their exact computation using Timed Boolean Functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Performance Through Hierarchy in Static Timing Verification
Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1 - Volume I
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Approximate timing analysis of combinational circuits under the XBD0 model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchical approach towards system level static timing verification of SoCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Considering zero-arrival time and block-arrival time in hierarchical functional timing analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
| Hi-index | 0.00 |
We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identification of false paths. We exploit hierarchy information to perform efficient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit c6288, which is difficult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAT. The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.