Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Estimation for maximum instantaneous current through supply lines for CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
ATPG for Noise-Induced Switch Failures in Domino Logic
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional timing analysis using ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient mechanism for performance optimization of variable-latency designs
Proceedings of the 44th annual Design Automation Conference
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
Fast computation of discharge current upper bounds for clustered power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of circuit dynamic behavior with timed ternary decision diagram
Proceedings of the International Conference on Computer-Aided Design
CCP: common case promotion for improved timing error resilience with energy efficiency
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Circuit timing analysis is important in various aspects of circuit optimization. The problem of finding input vectors achieving functional and temporal requirements is known as timed Automatic Test Pattern Generation (timed ATPG). A timed ATPG algorithm will return an input vector that satisfies functional and temporal requirements simultaneously when evaluated. Several previous works use timed ATPG as a core engine for solving problems related to timing analysis, such as crosstalk and maximum instantaneous current analysis. Despite the usefulness of timed ATPG, traditional timed ATPG is slow and unscalable for large circuits. In this paper, we present a very efficient way for timed ATPG. On average, our results are 8 times faster than the most recent work, and in some cases, up to 32 times faster.