Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
IEEE Transactions on Computers
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient Boolean characteristic function for fast timed ATPG
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven optimization using lookahead logic circuits
Proceedings of the 46th Annual Design Automation Conference
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Collaborative voltage scaling with online STA and variable-latency datapath
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case conditions could lead to inefficient resource use. It is possible to improve the throughput of such circuits by introducing variable latency. One of the existing realizations of variable-latency design style is based on Telescopic Units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally-designed hold logic in telescopic units may be inaccurate. We make use of the short path activation conditions to obtain more accurate hold logic than that commonly applied in the telescopic units. On average, our approach achieves a performance gain of 25.79% compared to 14.04%, which was reported in the previous works.